High resolution video displays are becoming more prevalent for modern data processing systems such as personal computer workstations and the like. As is well known, video displays achieve such higher resolution by increasing the density of picture elements ("pixels") within the screen area. Higher pixel density correlates to smaller pixel sizes, such that the resolution of the displayed image is increased. In addition, more recent video displays are utilizing more colors possible for each pixel. As a result, the display output of the workstation may be more accurate and lifelike, presenting the output of the computer or workstation in more useful and illustrative forms to the user.
The frequency at which conventional cathode-ray tube (CRT) displays must be updated or refreshed has a lower limit, generally around 60 Hz, although some display devices are refreshed at even faster rates. Update or refresh at a lower frequency will cause the display to flicker, and cause a moving image to jitter; each of these effects are, of course, annoying to the user and distract from the quality of the image presented by the computer. Since the period of time over which the entire display output can be written is thus fixed, higher resolution displays require a shorter time for presentation of each pixel to the monitor. For example, a 256 by 256 pixel display, updated at 60 Hz, requires one pixel of data every 0.25 microseconds, i.e., a pixel data rate of 4 MHz. A modern high resolution display having 1024 by 768 pixels, refreshed at the same frequency of 60 Hz, requires a pixel of data every 21 nanoseconds (pixel data rate of 47 MHz). Of course, faster frame rates will further increase the required pixel data rate. As a result, a major challenge in the design of high resolution displays is to provide the necessary high speed data processing and communication circuitry to output the pixel data at the proper data rates.
Referring now to FIG. 1, a first graphics subsystem according to the prior art will be described. According to this conventional system, video controller 10 is in communication with a host processor, such as a microprocessor, by way of host bus HBUS. Host bus HBUS communicates data from the host processor, through video controller 10, to video frame memory (VRAM) 14; VRAM 14 stores the data to be displayed on the output monitor, generally in bit-mapped or other well-known forms. Video controller 10 may be a special purpose microprocessor for controlling access between the host processor and VRAM 14, and generally executes graphics instructions such as line draw, block transfer, and the like; an example of such a type of video controller 10 is the TMS 34020 graphics system controller manufactured and sold by Texas Instruments Incorporated. Many large volume computer manufacturers prefer to implement video controller 10 as a custom integrated circuit, such as an application-specific integrated circuit (ASIC), customizing the functionality and performance of the graphics subsystem.
Video controller 10 is in communication with VRAM 14 via bus RDATA and control lines CTRL, in the conventional manner, as shown in FIG. 1. Video controller 10 also presents a clock input VLCK to VRAM 14, for controlling the rate at which data is presented at the output of VRAM 14. In this embodiment of the invention, VRAM 14 is a system of multiple memory integrated circuits, preferably video DRAM devices as are readily available in densities up to at least 1 Mbit. As well known in the art, such video DRAM devices include both a random access port and an independent serial access port. According to the system of FIG. 1, the random access ports of the video DRAM devices in VRAM 14 are coupled to bus RDATA in communication with video controller 14, and the serial output ports of the video DRAM devices in VRAM system 14 are coupled to video digital-to-analog converter (VDAC) 16. Clock input VCLK controls the rate at which data is clocked from the serial output of VRAM 14 to VDAC 16.
VDAC 16 is a conventional video DAC, such as the Bt473 True Color RAMDAC or the Bt477 Power-Down RAMDAC, each manufactured and sold by Brooktree Corporation. Modern VDACs, such as the Bt477, include not only the digital-to-analog circuitry required to convert a digital data stream into analog signals for application to a CRT monitor (not shown), but also include some amount of graphics data processing capability. For example, many conventional VDACs include color palette memories, so that the data presented to its input need not be the actual RGB (red-green-blue) data for conversion, but instead may be an index from which the VDAC generates the color information and appropriate data for presentation. Referring to FIG. 1, the RGB outputs of VDAC 16 are shown as comprising bus GDATA', and carry analog signals corresponding to the intensity of each color to be applied to the monitor screen, in the conventional manner.
In the conventional system of FIG. 1, timing control of the display is based on oscillator 12, which presents a clock signal to video controller 10. In these prior art systems, video controller 10 performs its operations according to the output of oscillator 12, and drives clock signal VCLK at its output. Clock signal VCLK is applied both to the serial clock input of VRAM 14, and also to VDAC 16 to latch the pixel video data on bus VDATA into VDAC 16 for conversion into the RGB data in the conventional manner. However, it should be noted that since the clock signal used to clock out the video data passes through video controller 10, and is also used to clock VRAM 14, the pixel clock rate at which VDAC 16 receives and presents each pixel's data is limited to the cycle time of VRAM 14, which is on the order of 33 MHz for the fastest video DRAM devices. Accordingly, the display resolution controllable by this system is necessarily limited.
It should be noted that one prior technique for overcoming this limitation on the pixel clock rate is to provide an external multiplexing device for receiving multiple pixels' data from VRAM 14. In such a system, the output of the external multiplexer is clocked at the pixel clock rate to present each pixel at the desired rate. However, this solution is quite expensive and impractical in today's technology, particularly considering the load presented by adding integrated circuit chips in the highest speed data path.
In addition, since the clock signal used to control the serial data output from VDAC 16 is generated indirectly from oscillator 12 by video controller 10, variations in the propagation delay of this clock signal must be taken into account in the design. Particularly for large VRAM systems 14, such as those necessary to present large numbers of colors, or true color output (requiring twenty-four parallel graphics output bits), the load of the serial clock inputs of memory devices in VRAM 14 requires relatively large buffering of clock output VCLK in video controller 10, further increasing the delay therethrough and its variability.
Referring now to FIGS. 2a and 2b, a second conventional graphics subsystem will now be described. This system is theoretically applicable to higher resolution displays, because the frequency of the clock applied to the video DAC is greater than that applied to the video DRAM devices. As shown in FIG. 2a, the output of a high speed oscillator 18 is applied directly to the clock input of VDAC 22, and VDAC 22 will generate a lower frequency clock for controlling video controller 20 and accesses from VRAM 14.
The system of FIG. 2a, similarly as the system of FIG. 1, includes video controller 20 for communication with the host processor (not shown), and with the random access port of VRAM 14 by way of bus RDATA and control lines CTRL; video controller 20 also generates the clock signal VCLK which controls the data output from the serial port of VRAM 14, which is applied to VDAC 22.
In the system of FIG. 2a, however, VDAC 22 includes latch 24 and multiplexer 26, so that the serial port of VRAM 14 may receive data for multiple pixels at a time. An example of VDAC 22 in this prior system is the Bt474 Triple 8-Bit 85 MHz RAMDAC manufactured and sold by Brooktree Corporation. High speed oscillator 18, which generates the video output clock (pixel clock) signal PCLK, is connected directly to VDAC 22 (i.e., not via video controller 20). Pixel clock signal PCLK is connected to multiplexer controller 28 to control the multiplexing of the pixel data, and also to divide-by-N circuit 27 which, via buffer 29, generates output clock signal OUTCLK for application to video controller 20. Clock signal OUTCLK also is connected internally to latch 24, and controls the latching of data from bus VDATA into VDAC 22. Multiplexer controller 28 controls multiplexer 26 to select the proper bits of latch 24 for application to palette/DAC circuitry 25, which generates the appropriate RGB analog signals on analog bus GDATA' to the display device, for example a monitor.
Video controller 20 includes clock logic circuitry 21 and buffer 23, for generating clock signal VCLK at the proper frequency and phase, such that the serial output data from VRAM 14 is applied to VDAC 22 at the appropriate time.
As a result of this multiplexed configuration, the VRAM 14 cycle time does not directly limit the pixel clock cycle time, as in the case of the system of FIG. 1. For example, if bus VDATA carries two pixels' worth of data, pixel clock signal PCLK can be at twice the frequency of clock signal VCLK (i.e, N equals 2, in divide-by-N circuit 29). Multiplexer controller 28 will select first one pixel, then the other, on successive cycles of pixel clock signal PCLK, with data for the next two pixels appearing on bus VDATA for latching into latch 24 during this time.
The timing of the operation of the system of FIG. 2a is shown in FIG. 2b, and will now be described in detail, for a 2:1 multiplexed case. The period of clock signal OUTCLK is shown as t.sub.cyc in FIG. 2b, generated by divide-by-2 circuit 27 in VDAC 22 to be twice the period of pixel clock signal PCLK (shown as t.sub.pcyc). Latch 24 in VDAC 22, in this example, latches in its data upon the rising edge of clock signal OUTCLK. Clock signal VCLK, generated by video controller 20 from clock signal OUTCLK, has the same frequency as clock signal OUTCLK but is delayed therefrom by the value t.sub.pd, corresponding to the propagation delay through clock logic 21 and buffer 23 therein. Upon the rising edge of clock signal VCLK, followed by the serial port access time t.sub.ac of VRAM 14, VRAM 14 presents data at its serial output. As noted hereinabove, since this is a 2:1 multiplexed case (i.e., two pixels of data are read from VRAM 14 at a time, for display by VDAC 22 one-by-one), data for two pixels are presented on bus VDATA after the access time t.sub.ac. In order that the data is accurately latched by latch 24 upon the rising edge of clock signal OUTCLK, the serial data on bus VDATA must be present a certain set-up time t.sub.su prior to the rising edge of clock signal OUTCLK.
In operation, as shown in FIG. 2b, the rising edge of clock signal OUTCLK latches two pixels of data (e.g., pixels n-2 and n-1) into latch 24. The next two rising edges of pixel clock signal PCLK cause the contents of the two latched pixels to be communicated (shown in FIG. 2b as digital signals GDATA) to DACs within VDAC 22 for presentation to the monitor as analog signals on analog bus GDATA'. During these two cycles of pixel clock signal PCLK, clock signal OUTCLK is communicated to video controller 20 for generation of clock signal VCLK, which is communicated to VRAM 14 for presentation of data for the next two pixels n, n+1.
In order for the system of FIGS. 2a and 2b to operate, the access of data from VRAM 14 must occur in time to be latched into latch 24 upon the next rising edge of clock signal OUTCLK. Referring to FIG. 2b, this requires the following relationship among the times shown therein: EQU t.sub.cyc .gtoreq.t.sub.pd +t.sub.ac +t.sub.su
with EQU N(t.sub.pcyc)=t.sub.cyc
For the example of FIG. 2b where N equals 2, and using typical times for t.sub.pd of 25 nsec, t.sub.ac of 25 nsec, and t.sub.su of 4 nsec, t.sub.pcyc must be 27 nsec or greater for proper operation. For 60 Hz display refresh, this limits the applicability of the system of FIG. 2a to a display no greater than 785 pixels on a side (where 2:1 multiplexing is used).
According to the above example, of course, greater multiplexing (e.g., 4:1 and 8:1) will allow the period of pixel clock signal PCLK to be much faster. However, the number of data bits presented for each pixel corresponds to the number of colors available for display (for an n-bit word, 2.sup.n colors may be selected). Accordingly, for the system of FIG. 2a, high resolution display requires limiting the available color choices, increasing the width of the bus carrying the pixel data, or limiting the spatial resolution of the display system.
Furthermore, the highest color selection in modern graphics systems utilizes twenty-four bits of information per pixel. This "true color" mode provides eight intensity bits for each of the red, green and blue guns of an RGB monitor. For conventional data paths of thirty-two bits, this true color mode precludes multiplexing of pixel data on the bus, requiring a value of one for N in the above-described example. Given the examples of propagation time, access time and setup time above in the system of FIG. 2a, operation of the system in non-multiplexed mode limits the pixel clock period to 54 nsec or longer, further limiting the display resolution available.
It is therefore an object of this invention to provide a video display system capable of handling high data rates compatible with high resolution display monitors.
It is a further object of this invention to provide such a system which allows for selectable multiplexing schemes, including 1:1 multiplexing, providing selectable display resolution within the system timing requirements.
It is a further object of this invention to provide a video DAC useful in such a system.
It is a further object of this invention to provide such a system which allows for extremely wide pixel data words, such as necessary for "true" color display.
Other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the claims.